Constructing Neural Branch Prediction with Memristive Device

Abstract

In superscalar computers, average branch instruction latency is crucial to the overall performance of the computer. Among all the branch predictors that have been proposed, neural branch predictors tend to have a better performance than traditional branch predictors, especially on benchmarks with long branch history correlation. However, huge latency of training process and power overhead makes it impossible to integrate neural branch predictors with modern computer chips. On April 30, 2008, HP Labs announced the development of switching memristor. The electrical property of memristor makes it a promising candidate of building fast neural branch predictors. We propose architectural algorithm enhancement as well as circuit level design with memristors to overcome the shortcomings of existing neural branch predictions.