OpenSPLySER: The Integrated OpenSPARC and DySER Design

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dc.contributor.authorBenson, Jesseen_US
dc.contributor.authorCofell, Ryanen_US
dc.contributor.authorFrericks, Chrisen_US
dc.contributor.authorHo, Chen-Hanen_US
dc.contributor.authorSankaralingam, Karthikeyanen_US
dc.date.accessioned2012-03-15T17:25:23Z
dc.date.available2012-03-15T17:25:23Z
dc.date.created2011en_US
dc.date.issued2011en_US
dc.description.abstractThe Dynamically Synthesized Execution (DySE) model has been proposed to improve the energy efficiency and performance of general purpose programmable processors. We describe how a DySE Resource (DySER) block can be integrated into a processor pipeline. The block size can be adjusted based on design constraints, but we integrate an 8x8 functional unit array into a simple in-order OpenSPARC T1 pipeline. The instruction set changes and the microarchitectural interface between the DySER block and processor are described.en_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.citationTR1685en_US
dc.identifier.urihttp://digital.library.wisc.edu/1793/60728
dc.publisherUniversity of Wisconsin-Madison Department of Computer Sciencesen_US
dc.titleOpenSPLySER: The Integrated OpenSPARC and DySER Designen_US
dc.typeTechnical Reporten_US

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