Studying Hybrid Von-Neumann/Dataflow Execution Models

Abstract

Hardware specialization is becoming a promising paradigm for future microprocessors. Unfortunately, by its very nature, the exploration of specialization ideas, (the artifact is dubbed an ?accelerator?) are developed, evaluated, and published as end-to-end vertical silos spanning application, language/compiler, and hardware architecture, with per-accelerator customized tools, and little opportunity for cross-application of ideas from one accelerator into another.

This paper develops a novel program representation suitable for the hardware specialization paradigm, called the transformable dependence graph (TDG), which combines semantic information about program properties and low-level hardware events (cache misses, branch mis-predictions, resource hazards, energy expended by hardware events) in a single representation. We demonstrate that the TDG is a feasible, simple, and accurate modeling technique for transparent specialization approaches, enabling architectures to be compared and analyzed easily in a single framework. We demonstrate models for four previously proposed accelerators.