Processor Interconnection Strategies

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dc.contributor.authorFinkel, Raphaelen_US
dc.contributor.authorSolomon, Marvinen_US
dc.date.accessioned2012-03-15T16:27:32Z
dc.date.available2012-03-15T16:27:32Z
dc.date.created1977en_US
dc.date.issued1977
dc.description.abstractIn this paper we describe four topologies for interconnecting many identical processors into a computer network. Each topology is investigated with respect to average interprocessor distance, bus load, and routing algorithms. These topologies share the property that each processor can communicate directly with at most a small number of other processorsen_US
dc.format.mimetypeapplication/pdfen_US
dc.identifier.citationTR301
dc.identifier.urihttp://digital.library.wisc.edu/1793/58044
dc.publisherUniversity of Wisconsin-Madison Department of Computer Sciencesen_US
dc.titleProcessor Interconnection Strategiesen_US
dc.typeTechnical Reporten_US

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