Dynamical Synthesized Execution Resources (DySER) Deisgn Specification
| dc.contributor.advisor | Hu, Yu Hen | |
| dc.contributor.author | Ho, Chenhan | |
| dc.date.accessioned | 2011-02-09T21:26:37Z | |
| dc.date.available | 2011-02-09T21:26:37Z | |
| dc.date.issued | 2010-12-15 | |
| dc.description.abstract | Because of the limitations of the fabrication technology, many specialized hardwares are purposed for energy efficiency and performance. Unlike the traditional Von Neumann machine, the specialized hardwares focus on the integration of large scope execution, which often requires the cooperation of software and microarchitecture support to work. Unlike the specialized nature of previous work, we developed a generalized in-core hardware, Dynamical Synthesized Execution Resources, to broaden the intuition of specialized hardware. In this work, we define the microarchitecture of the DySER.We also discuss the interface to integrate the DySER into a basic in-order SPARC-like pipeline or a out-of-order Intel Nehalem-like pipeline. In addition, we describe some corner cases which would become problematic in the Dynamic Synthesis Execution (DySE) model. | en |
| dc.identifier.uri | http://digital.library.wisc.edu/1793/48288 | |
| dc.title | Dynamical Synthesized Execution Resources (DySER) Deisgn Specification | en |
| dc.type | Project Report | en |
| thesis.degree.discipline | Electrical Engineering | en |
| thesis.degree.level | MS | en |
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